An assembly, inspection, test & integration risk screening of the ACube "PORTATILE" · NXP T2080 motherboard, checked against the IPC/J-STD family. This is not a manufacturing release review.
Taken directly from the board's released placement data: 2,191 placements — 680 top / 1,511 bottom, SMD 2,147 / THT 24 / mixed 5. Largest device U1 (896-ball, 0.8 mm pitch, 25 mm). The build is bottom-side heavy, which drives several findings.
Prototype build may proceed only after the pre-build blockers close; pilot and volume are not approved.
| Decision | Disposition |
|---|---|
| Engineering prototype (design) | CONDITIONAL |
| PCB quotation-ready | NO |
| PCB fabrication-ready | NO |
| PCBA prototype process | CONDITIONAL |
| Pilot production | NO |
| Volume production | NO |
| ID | Finding | S | O | D | AP | Standard | Recommended action |
|---|---|---|---|---|---|---|---|
| DFA-01 | No panelization / assembly-DFM package; no assembly sequence, fixture or takt defined. | 6 | 6 | 5 | High | IPC-A-610 | Author assembly flow + panel + fixtures |
| DFA-02 | Thermal-module clamp lands on U1 BGA; spring-screw sequence/torque undefined → board flex / joint damage. | 9 | 5 | 7 | High | IPC-7095 | Captive screws, marked sequence, torque, strain-gauge validation |
| DFA-03 | BGA/QFN process controls (X-ray, SPI, MSL) not evidenced for U1 + U50/U76 LGA + 17 QFN. | 8 | 5 | 7 | High | IPC-7095 · 7093 | Define X-ray criteria + SPI + MSL controls |
| PROC-07 | Bottom-side-heavy build: 1,511 of 2,191 placements on bottom → bottom parts see 2nd reflow; retention/adhesive risk. | 6 | 5 | 5 | Medium | J-STD-001 | Double-sided reflow profile; bottom-side mass/adhesive check |
| DFA-06 | Customer ports (HDMI J19 SMD, DC-in, USB/RJ45) may react mating force through solder — load path not analysed. | 7 | 5 | 6 | High | IPC-A-610 | Connector load-path analysis + enclosure support |
| DFT-01 | Real ICT node coverage unknown: probe side not encoded; only 6.4% dedicated-TP coverage; 209 no-access nets. | 7 | 6 | 7 | High | IPC-9252 / D-356 | DFT bottom-side access study; boundary-scan (J3 JTAG) |
| BLD-01 | No pilot-build evidence: no yield, defect pareto or process-capability data exists. | 7 | 7 | 6 | High | — | Run EVT/DVT pilot with KPI capture before any volume decision |
The DFA readiness scorecard averages ≈ 3.5 / 5 with multiple pre-build High categories open (thermal-module error-proofing, BGA process controls, test access). Quantitative analyses not yet performed — fastener schedule, connector load-path, thermal-clamp/board-strain, tolerance stacks — are tracked as open in the workbook; some may drive layout or mechanical redesign, so the earlier claim that "all high risks are documentation gaps" is withdrawn.
Download the evidence workbook (XLSX) →
Reviewed design: the open-hardware GNU/Linux PowerPC Notebook by Roberto Innocenti & the Power Progress Community — powerpc-notebook.org · design files (GitLab). Product Engineer LLC is independent and not affiliated with the project.
Every figure and finding on this page comes directly from the board's own released design data — the placement list, the ODB++ CAD netlist, the Gerber solder-paste layers, the released BOM and the mechanical review. Every figure is reproducible by re-running the same extraction against the released design package, and each conclusion is checked against the manufacturing standards below.
Design data © the Power Progress Community (open hardware). Detailed source-data provenance and per-finding citations are recorded in the accompanying evidence workbook.